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www.irf.com ? 2012 international rectifie r february 22, 2012 IRS2500s transition mode pfc control ic features ? pfc control ic ? boost or flyback converter modes ? critical-conduction / transition mode operation ? over-current protection ? static and dynamic dc bus overvoltage protection ? micropower startup (<50 a) ? low quiescent current (2.5ma) ? latch immunity and esd protection ? wide range pfc for universal ac line input ? low thd ? open load over voltage protection ? noise immunity typical applications ? switched mode power supplies ? electronic ballasts ? led drivers product summary topology boost / flyback i o+ & i o- (typical) 500 / 500 ma t r & t f (typical) 60 / 30 ns packages 8-lead soic typical connection diagram
IRS2500s www.irf.com ? 2012 international rectifie r 2 table of contents page description 3 qualification information 5 absolute maximum ratings 6 recommended operating conditions 6 electrical characteristics 7 functional block diagram 9 input/output pin equivalent circuit diagram 10 lead definitions 11 lead assignments 11 application information and additional details 12 package details 19 tape and reel details 20 part marking information 21 ordering information 22
IRS2500s www.irf.com ? 2012 international rectifie r 3 description the IRS2500 is a fully integrated, fully protected pf c smps control ic designed to drive boost or flyback switching regulators providing high power factor. ty pical applications are pfc pre-regulators for smps and electronic ballasts for fluorescent or hid lighting as well as single stage flyback converters widely used in low power led drivers. the IRS2500 is pin compatible with most industry standard critical conduction or transition mode pfc control ic with additional improv ements to increase performance. the pfc circuitry provides high pf, low thd and stable dc bus regul ation over a wide line/load range. the IRS2500 protection features include cycle by cycle over-current protection and output over voltage protection.
IRS2500s www.irf.com ? 2012 international rectifie r 4 typical application diagram dbus t1 br1 cin mpfc rpfc rv1 rv2 cvout roc IRS2500 1 2 3 4 8 7 6 5 inv comp vdc oc zx com out vcc cf rf cvcc dvcc rs ic3a ic1 ri rpu ic2 din rin rdc vreg cvreg ic3b rd1 rd2 rd3 rvfb cvfb rifb cifb +5v rzx out+ out- ac line input cf rpd ccomp rfb1 rfb2 rii rsh
IRS2500s www.irf.com ? 2012 international rectifie r 5 qualification information ? qualification level industrial ?? comments: this family of ic s has passed jedec?s industrial qualification. ir?s consumer qualification level is granted by extension of the higher industrial level. moisture sensitivity level msl2 ??? 260c (per ipc/jedec j-std-020) esd machine model class b (per jedec standard jesd22-a115) human body model class 2 (per eia/jedec standard eia/jesd22-a114) ic latch-up test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should t he user have such requirements. please contact your international rectifier sales r epresentative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales repr esentative for further information.
IRS2500s www.irf.com ? 2012 international rectifie r 6 absolute maximum ratings absolute maximum ratings indicate sustained limit s beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to co m, all currents are defined positive into any lead. the thermal resistance and power dissipation ra tings are measured under board mounted and still air conditions. s y mbol definition min. max. unit s vcc supply voltage ? -0.3 vclamp v out gate driver output voltage -0.3 v cc + 0.3 v io max maximum allowable output current (out) due to external power transistor miller effect -500 500 ma icc vcc current 0 25 ma v comp comp pin voltage -0.3 v cc + 0.3 v voc oc pin voltage v vbus vbus pin voltage -0.3 7.0 vdc vdc pin voltage vzx zx pin voltage i comp comp pin current -5 5 ma i zx zx pin current i oc oc pin current p d package power dissipation @ ta +25oc --- 0.625 w r ja thermal resistance, junction to ambient --- 128 oc/w t j junction temperature -55 150 oc t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) --- 300 recommended operating conditions for proper operation the device should be used within recommended conditions. s y mbol definition min. max. units v cc supply voltage ? v ccuv+ v clamp v i cc v cc supply current 0 10 ma i oc oc pin current -1 1 i zx zx pin current t j junction temperature -25 125 oc ? : this ic contains a zener clamp structure between the chip vcc and com which has a nominal breakdown voltage of 20v. this supply pin should not be driven by a dc, lo w impedance power source greater than the vclamp specified in the electrical characteristics section.
IRS2500s www.irf.com ? 2012 international rectifie r 7 electrical characteristics v cc = 14 v +/- 0.25 v, c out =1000 pf, c vcc =0.1 f, t a =25 c unless otherwise specified. symbol definition min typ max units test conditions supply characteristics v ccuv + v cc supply undervoltage positive going threshold 11.5 12.5 13.5 v ccuv - v cc supply undervoltage negative going threshold 9.5 10.5 11.5 v uvhys v cc supply undervoltage lockout h y steresis 1.5 2.0 3.0 i qccuv uvlo mode v cc quiescent current --- 30 --- ua vcc = 8v i cc v cc supply current --- 2.3 5.0 ma vbus=2.5v pfc off time = 5us v clamp v cc zener clamp voltage --- 20.0 --- v i cc = 10ma error amplifier characteristics i comp source comp pin error amplifier output current sourcin g --- 10 --- ma v vbus = 2.4v vcomp=4.0v i comp sink comp pin error amplifier output current sinkin g --- -23 --- v vbus = 2.6v vcomp=4.0v v compoh error amplifier output voltage swing (high state ) --- 6.0 --- v vbus=2.0v icomp=-0.5m a v compol error amplifier output voltage swing (low state ) --- 0.25 --- vbus=3.0v icomp=+0.5m a vcompfl t error amplifier output voltage in fault mode --- 0 --- vbus=3.0v ivbus input bias current --- --- -1 ua vbus=0 to 3v gv voltage gain 60 80 --- db open loop gb bandwidth --- 1 --- mhz control characteristics v vbus vbus internal reference voltage 2.46 2.5 2.54 v v comp = 4.0v v zx+ zx pin threshold voltage (arm) --- 1.6 --- v zx- zx pin threshold voltage (trigger) --- 0.7 --- v zxclamp zx pin clamp voltage (high state) --- 5.2 --- i zx = 1ma vdcclamp vdc pin clamp voltage --- 5.2 --- idc = 1ma t blank oc pin current-sensing blank time --- 320 --- ns vbus=2.5v vcomp=4.0v t wd pfc watch-dog pulse interval --- 400 --- us zx = 0,v comp = 4.0v t onmin pfc minimum on time --- 0.3 --- us zx = 0,v comp = 0.25v t onmax pfc maximum on time 10 50 --- us zx = 0,v comp = 6.0v, vdc = 2v
IRS2500s www.irf.com ? 2012 international rectifie r 8 electrical characteristics (cont?d) v cc = 14v +/- 0.25v, c out = 1000pf, v comp = v oc = vbus = vzx = 0v, t a =25c unless otherwise specified. protection circuitry characteristics v octh oc pin over-current sense threshold 0.93 1.1 1.22 v v vbusov vbus over-voltage comparator threshold 2.7 guaranteed by desi g n v vbusov hys vbus over-voltage comparator h y steresis 50 100 150 mv guaranteed by desi g n icompov+ dynamic over-voltage detection threshold 30 ua icompov- dynamic over-voltage detection reset 8 gate driver output characteristics v ol low-level output voltage --- 0 100 mv i o = 0 v oh high-level output voltage --- 0 11 v i o = 0 t r turn-on rise time --- 60 110 ns t f turn-off fall time --- 30 70 i0+ source current --- 500 --- ma i0- sink current --- 500 ---
IRS2500s www.irf.com ? 2012 international rectifie r 9 functional block diagram out comp zx vzxclamp vzx q s r2 q r1 q s rq vcc oc vcc com vbus 8 4 1 7 2 5 watchdog timer 6 ovp vvbusov vvbus vclamp vocth blank time vdc 3 on time modulator uvlo vdcclamp
IRS2500s www.irf.com ? 2012 international rectifie r 10 input/output pin equivalent circuit diagrams
IRS2500s www.irf.com ? 2012 international rectifie r 11 lead definitions symbol description vbus dc bus sensing input comp pfc error amplifier compensation vdc full wave voltage input oc pfc current sensing input zx pfc zero-crossing detection com ic power & signal ground out gate drive output vcc logic & low-side gate driver supply lead assignments 7 6 5 IRS2500 com 1 2 3 vbus 4 comp out zx vcc 8 oc vdc
IRS2500s www.irf.com ? 2012 international rectifie r 12 application information and additional details power factor correction is required in many electrical appliances in or der to minimize reactive current losses in ac power transmission lines. the degree to which an electronic circuit matches an ideal purely resistive load is measured by the phase shift (displacement) between the input voltage and input current and the amount of current waveform distortion. in other words how well the shape of the input current waveform matches the shape of the sinusoidal input voltage. the power factor (pf) is defined as the ratio between real power and apparent power with the maximum value of 1.0 representing a totally resistive load where the current waveform shape matches the voltage waveform shape exactly. the distortion of the input curr ent waveform is quantified by the total harmonic distortion (thd), which is the sum of all harmonic content of the waveform expressed as a percentage. an ideal power factor of 1.0 corresponds to zero phase shift and a thd of 0% representing a purely sinusoidal input current waveform in phase with the line voltage. the lower the power factor the more current is needed to supply the same power to the load, which results is higher conduction losses in transmission lines. for this reason it is desirable to have a high pf and a low thd. to achieve this, the IRS2500 implements an active power factor correction (pfc) circuit. the control method implemented in the IRS2500 may be used in a boost converter (figure 8) or a low power single stage flyback converter for small power supplies or led drivers. the IRS2500 operates in critical-conduction mode (crcm), also known as transition mode. this means that during each switching cycle of the pfc mosfet, the circuit waits until the inductor current discharges to zero before turning the pfc mosfet on again. the pfc mosfet is turned on and off at a much higher frequency (>10khz) than the line input frequency (50 to 60hz). cbus + (+) (-) mpfc lpfc dpfc dc bus figure 8: boost converter circuit. when the switch mpfc is turned on, the inductor lpfc is connected between the rectified line input (+) and (-) causing the current in lpfc to increase linearly. when mpfc is turned off, lpfc is connected between the rect ified line input (+) and the dc bus capacitor cbus through diode dpfc. the stored energy in lpfc is transferred to the output, supplying a current into cbus. mpfc is turned on and off at a high frequency and the voltage on cbus charges up to a specified voltage. the voltage feedback loop of the IRS2500 regulates the output to the desired voltage by continuously monitoring the dc output and adjusting the on-time of mpfc accordingly. if the output voltage is too high, the on-time is decreased and if it is too low, the on-time is increased. this negative feedback control loop operates with a slow loop speed and a low loop gain such that the average inductor current smoothly follows the low- frequency line input voltage to obtain high power factor and low thd. the loop speed is intentionally slow with respect to the ac line frequency so that there is no appreciable change in the on time during a single line half cycle. this allows the current to follow shape of the sinusoidal voltage. v, i t figure 9: sinusoidal line input voltage (solid line), triangular pfc inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the ac line input voltage . corrections to the output voltage therefore require several line cycles. with a fixed on-time, and an off- time determined by the inductor current discharging to zero, the result is a system where the switching frequency is free-running and constantly changing from a high frequency near the zero crossing of the ac input line voltage, to a lower frequency at the peaks (figure 9). when the line input voltage is low (near the zero crossing), the inductor current will increase only a small amount and the discharge time will be short resulting in a high switching frequency. when the input line voltage is high (near the peak), the inductor current will charge up to a much higher
IRS2500s www.irf.com ? 2012 international rectifie r 13 level and the discharge time will be longer giving a lower switching frequency. the pfc control circuit of the IRS2500 (figure 10) includes six control pins: vbus, comp, zx, out, vdc and oc. the vbus pin measures the dc bus voltage through an external resistor voltage divider. the comp pin voltage determines the on- time of mpfc and sets the feedback loop response speed with an external rc integrator. the zx pin detects when the inductor current discharges to zero each switching cycle using a secondary winding from the pfc inductor. the out pin is the low-side gate driver output for the external mosfet, mpfc. the vdc pin senses the line input cycle providing phase information to control the on time modulation described in the next section. the oc pin senses the current flowing through mpfc and performs cycle-by-cycle over- current protection. rvbus1 rvbus2 rvbus ccomp lpfc mpfc rpfc dfpc cbus (+) (-) rzx pfc control vbus comp out zx com oc roc rdc rin vdc figure 10: IRS2500 simplified pfc control circuit. the vbus pin is compared with a fixed internal 2.5v reference voltage fo r regulating the dc output voltage (figure 11). the feedback loop error amplifier increases or decreases the comp pin voltage. the resulting voltage on the comp pin sets the threshold for the charging of the internal timing capacitor (c1, figure 11) and therefore determines the on-time of mpfc. the error amplifier operates at a slow loop speed preventing rapid changes in pwm duty cycle during a single input line cycle. this prevents distortion achieving high power factor and low thd. 5 2 1 q s rq 2.0v vbus comp zx 5.1v 2.5v 2.75 7 out q s r2 q r1 comp3 comp4 comp5 rs3 rs4 vcc m1 watch dog timer m2 c1 4 oc 1.2v on time modulator 3 vdc figure 11: IRS2500 detailed pfc control circuit. the off-time of mpfc is determined by the time it takes the lpfc current to discharge to zero. the zero current level is detected by a secondary winding on lpfc that is connected to the zx pin through an external current limiting resistor rzx. a positive-going edge exceeding the internal threshold vzx+ signals the beginning of the off- time. a negative-going edge on the zx pin falling below vzx- will occur when the lpfc current discharges to zero, which signals the end of the off- time and mpfc is turned on again (figure 12). the zx pin is internally biased to ensure that the voltage detected from the inductor drops fully to zero before triggering the next pwm cycle. a wide hysteresis prevents false triggering by ringing oscillations. the cycle repeats itself indefinitely until the IRS2500 is disabled through an over-voltage condition on the dc bus or if the negative transition of zx pin voltage does not occur. should the negative edge on the zx pin not occur, mpfc will remain off until the watch-dog timer forces a turn-on of mpfc for an on-time duration programmed by the voltage on the comp pin. the watch-dog pulses occur every 300-400us (twd) indefinitely until a correct positive and negative-going signal is detected at the zx pin and normal operation is resumed. should the oc pin voltage exceed the vocth over-current threshold during the on-time the gate drive output will turn off. the circuit will then wait for a negative-goi ng transition on the zx pin or a forced turn-on from the watch-dog timer to turn the output on again.
IRS2500s www.irf.com ? 2012 international rectifie r 14 i lpfc out zx oc vocth . . . . . . . . . . . . figure 12: inductor current, out pin, zx pin and oc pin timing diagram. on-time modulation circuit a fixed on-time of mpfc ov er an entire cycle of the line input voltage produces a peak inductor current which naturally follows the sinusoidal shape of the line input voltage. the smoothed, averaged line input current is in phase with the line input voltage for high power factor but a high total harmonic distortion (thd), as well as individual higher harmonics, of the current ar e still possible. this is mostly due to cross-over distortion of the line current near the zero-cro ssings of the line input voltage. to achieve low harmonics that are acceptable for compliance with international standards and general market requirements, an additional on-time modulation circuit has been added to the pfc control. this circuit dynamically increases the on-time of mpfc as the line input voltage nears the zero-crossings (figure 13). this causes the peak lpfc current, and therefore the smoothed line input current, to increase near the zero-crossings of the line input voltage. this reduces the amount of cro ss-over distortion in the line input current which reduces the thd and higher harmonics. the on time modulation function is controlled via the vdc input. the full wave rectified voltage from the bridge rectifier is divided down by rin and rdc to provide an input with a peak voltage of approximately 1v at 90vac input and 3v at 277vac. cdc is added to remove noise from the signal, the value is typically 10nf. the on time modulation function is not required in some applications. in such cases the vdc input should be tied to vcc through a 10k resistor. 0 0 i lpfc out pin near peak region of rectified ac line near zero-crossing region of rectified ac line figure 13: on-time modulation circuit timing diagram. output over-voltage protection the IRS2500 incorporates both static and dynamic overvoltage protection. static over voltage protection monitors the feedback voltage at the vbus pin and disables the gate drive output if this voltage exceeds the target voltage by 8%. this is activated by an internal comparator set to detect a threshold of 2.7v, which is 8% above the regulation threshold of 2.5v. however, under startup condition or when a load is removed from the output t he error amplifier output voltage at the comp pin swings low. since the compensation capacitor ccomp is connected from this output back to the vbus input a current will flow during the comp voltage transition. this pulls down the vbus voltage, which allows the output voltage to exceed the desired regulation level during the transition and results in an overshoot before the voltage at the vbus input exceeds the regulation threshold. in order to compensate fo r this effect, the IRS2500 includes dynamic detection of the error amplifier output current. during a swing in the negative direction the error amplif ier output current peaks at a much high level than the level during steady state operation. this higher current is internally detected and triggers the overvoltage protection circuitry disabling the pwm output until the error amplifier output has settled to a new level. this prevents the output voltage from overshooting the desired level by a significant amount under the transient conditions described. for this reason the loop should be designed such that voltage ripple at comp is minimized duri ng steady state operation.
IRS2500s www.irf.com ? 2012 international rectifie r 15 pcb layout guidelines for correct operation of the IRS2500, the pcb should be designed to avoid noise coupling to the control inputs and ground loops. by following the recommendations listed here potential issues will be avoided: 1. the circuit signal and power grounds should be joined together at one point only. the signal ground should be a star point located close to the com pin of the IRS2500. 2. the point at which the signal ground is connected to the power ground is recommended to be at the current sense resistor (roc) ground. 3. a 0.1 f noise decoupling capacitor should be located between the vcc and com pins of the IRS2500 located as close to the ic as possible. 4. all traces to the vbus input should be as short as possible. this means that resistors and capacitors that are connected to this input should be located as close to the IRS2500 as possible. the voltage feedback divider resistor connected to com should be connected to a signal ground close to the com pin. 5. traces carrying high voltage switching signals such as those connected to the mosfet drain or gate drive signals should not be located close to traces connected directly to the vbus input. 6. the divider network resistor (rdc) and filter capacitor (cdc) connected to the vdc input of the IRS2500 should be located as closely to the ic as possible with the grounded end connected to the circuit signal ground. 7. the compensation capacitor ccomp should be located close to the IRS2500 with short traces leading to the vbus and comp pins. 8. the over current detecti on filter resistor (roc) and capacitor (coc) should be located as close to the IRS2500 as possible with coc connected to the circuit signal ground. 9. the zero crossing detection resistor should be located close to the IRS2500 if possible to prevent possible noise appearing at this input. figure 14: layout example figure 14 shows a layout where the IRS2500 is located on the bottom side of the pcb. the bottom side traces are shown in red and the top side traces in pale blue. the circuit power ground can be seen at the c2 gnd node with the signal ground star point is located at the junction between rpfc6 and cpfc4 to the left of the IRS2500 (ic1). (note that the component designators in this example are different from those used in the datasheet schematics) the traces from ic1 pin 6, rpfc3 and cpfc1 (the vdc divider low side) all run directly to the star point without crossing any other grounds. the signal ground is connected to the power ground at the current sense resistor. a large trace can be seen running from the star point off the left to where the mosfet is situated ( not shown). this is the single point where the signal and power grounds are connected. the vcc supply decoupling capacitor shown in this ex ample is cpfc4, which is located very close to the IRS2500 and grounded directly to the signal ground star point. traces leading to pin 1 (vbus) are all short and components connected to pin 1 (rpfc5, rpfc6 and rpfc7) are all located close to ic1. there are no traces connected to high voltage switching nodes located anywhere close to pin 1. the board layout shown in figure 14 complies with all of the guidelines stated enabling optimum operation of the IRS2500.
IRS2500s www.irf.com ? 2012 international rectifie r 16 pfc design equations (for boost converter) step1: calculate pfc inductor value: vbus p f vac vac vbus l out min min min pfc ? ? ? ? ? ? ? = 2 ) 2 ( 2 [henries] (1) where, vbus = dc bus voltage min vac = minimum rms ac input voltage = pfc efficiency (typically 0.95) min f = minimum pfc switching frequency at minimum ac input voltage out p = ballast output power step 2: calculate peak pfc inductor current: ? ? ? = min out pk vac p i 2 2 [amps peak] (2) note: the pfc inductor must not saturate at pk i over the specified ballast operating temperature range. proper core sizing and air-gapping should be consider ed in the inductor design. step 3: calculate pfc over-current resistor roc value: pk oc i vocth r = where vocth = 1.1v [ohms] (3) step 4: calculate start-up resistor rvcc value: iqccuv vac r pk min vcc 10 + = [ohms] (4)
IRS2500s www.irf.com ? 2012 international rectifie r 17 graph 1: vccuv+ vs. temperature graph 3: iqccuv vs. temperature graph 2: icc vs. temperature graph 4: vclamp vs. temperature 0 2 4 6 8 10 12 14 \ 25 0 25 50 75 100 125 temp ? c vccuv ? (+/ \ ) vccuv+ vccuv \ 0 0.5 1 1.5 2 2.5 \ 25 0 25 50 75 100 125 temp ? c icc ? ( ? ma) 0 20 40 60 80 100 120 \ 25 0 25 50 75 100 125 temp ? c iqccuv ? (ua) 20 20.2 20.4 20.6 20.8 21 21.2 21.4 21.6 21.8 22 \ 25 0 25 50 75 100 125 temp ? c vclamp ? (v)
IRS2500s www.irf.com ? 2012 international rectifie r 18 graph 5: vbus reference vs. temperature 40 41 42 43 44 45 46 47 48 49 50 \ 25 0 25 50 75 100 125 temp ? c pfc ? ton ? max ? (us) graph 7: pfc ton max (us) graph 6: watch dog interval vs. temperature package details 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 \ 25 0 25 50 75 100 125 temp ? c vbus ? (v) 0 50 100 150 200 250 300 350 400 450 500 \ 25 0 25 50 75 100 125 temp ? c watch ? dog ? interval ? (us)
IRS2500s www.irf.com ? 2012 international rectifie r 19
IRS2500s www.irf.com ? 2012 international rectifie r 20 tape and reel details e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c carrier tape dimension for 8soicn code minmaxminmax a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5.45 5.55 0.214 0.218 e 6.30 6.50 0.248 0.255 f 5.10 5.30 0.200 0.208 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 metric imperial
IRS2500s www.irf.com ? 2012 international rectifie r 21 part marking information
IRS2500s www.irf.com ? 2012 international rectifie r 22 ordering information base part number package type standard pack complete part number form quantity IRS2500 soic8 tube/bulk 95 IRS2500spbf tape and reel 2500 IRS2500strpbf the information provided in this document is believed to be accu rate and reliable. however, international rectifier assumes no responsibility for the consequences of the use of this information. international rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result fr om the use of this information. no license is granted by imp lication or otherwise under any patent or patent rights of international rectif ier. the specifications ment ioned in this document are subj ect to change without notice. this document supersedes and replaces all inform ation previously supplied. for technical support, please contact ir?s technical assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105

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